Gate array arrangement
US4811073A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 1988 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Apr 18, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
Abstract
A gate array arrangement formed on a semiconductor chip includes a plurality of I/O cells aligned along the four sides of the chip and a plurality of basic cells aligned in a plurality of rows extending parallelly to each other. A ground bus line and a power bus line extend in a space between the I/O cells and basic cells. The lines from the I/O cells are connected to the bus lines, and lines from basic cells are connected to bus lines. In this manner, the power supply lines between the I/O cells and basic cells are connected indirectly through the bus line, thereby allowing the determination of pitch of the I/O cells and pitch of basic cells independently of each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.