Multiple microprocessor watchdog system
US4811200A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1987 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | May 12, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A main microprocessor A (11) provides data to a display formatter microprocessor B (12) via a data bus (13). Microprocessor B provides data and latch (activity) pulses (34A) to a visual display (27) comprising a number of individual display devices (28-30) which are sequentially excited by data obtained from microprocessor B. An external activity detector (38), in response to an absence of the latch pulses of microprocessor B for a predetermined time, generates a reset signal (40) for resetting the microprocessor A. In response to being reset, microprocessor A provides an output control signal (at 20) which results in the resetting of the microprocessor B. If microprocessor B determines that microprocessor A is not properly providing data to it, microprocessor B will terminate generating the latch pulses (34A). The preceding configuration results in each of the microprocessors effectively monitoring the operation of the other microprocessor so as to insure proper system operation. Therefore, this system properly resets itself in response to any of a large number of different failures which may occur in either of the microprocessors, and this is accomplished with a minimum of additi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.