Direct memory access and display system
US4811204A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 1984 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Aug 16, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system including a central processing unit which connects to two or more buses. The buses include a memory bus connected to a main store, and to two or more I/O devices sharing common control for accesses to the main store. Priority of transfers over the memory bus is determined by priority circuit in a two-way priority between the processing unit and the common I/O devices on the memory bus. One common I/O devices is a display unit and the other common I/O device is a direct memory access disk unit. The display is periodically refreshed. Priority is always granted to the display device. Priority is granted to the disk device as a supplement to a access by the display device. The direct memory access device piggybacks on the priority of the display device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.