Pipeline display control apparatus with logic for blocking graphics processor accesses to shared memory during selected main processor graphics operations
US4811205A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1985 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Jun 24, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A graphics display apparatus employs a general purpose or main microprocessor providing general control of the apparatus including receiving high-level graphic orders defining a desired graphic image from a host processor and dedicated graphics microprocessor connected to receive low-level graphic orders from the general microprocessor along a pipeline constituted by a shared buffer store. Pipeline control logic controls the pipeline by blocking the graphics processor which generally operates more quickly than the general processor until the latter has completed computation of all the low-level orders associated with a particular high-level order. The front-of-screen performance can be further improved by backing up the pipeline to repeat certain low-level orders rather than by obtaining these repeated orders by recomputation. Graphics hardware controlled by the graphics processor loads appropriate bit patterns into an all points addressable refresh buffer for subsequent display on a cathode ray tube monitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.