Distributed arithmetic realization of second-order normal-form digital filter
US4811262A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 1986 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Sep 19, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed distributed-arithmetic realization of a second-order normal-form digital filter includes a filter input, a filter output, and a memory. The memory has a first input, a second input, and a third input. The first memory input is connected to the filter input. The memory also has a first output, a second output, and a third output. The digital filter additionally includes a first adder having an input connected to the first memory output, and having its output connected to the filter output. A second adder has an input connected to the second memory output, and has its output connected to the second memory input. A third adder has an input connected to the third memory output and has its output connected to the third memory input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.