Digital signal processor with addressable and shifting memory
US4811267A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 1988 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Feb 29, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital signal processor includes a digital memory, a controller, an arithmetic operation unit and an interconnecting bus. The memory includes a shift register having an addressable output for storing values which are supplied to a multiplier circuit of the arithmetic operation unit. Use of the shift register provides a data delay minimizing the number of instructions required to implement delay processing. In the arithmetic operation unit, the output from the multiplier is connected to an arithmetic logic unit which, in turn, is connected to an accumulator. The accumulator temporarily stores data from the arithmetic logic unit and output the result onto the data bus. The operations of the signal process are directed by the controller which includes a program memory, an instruction register, and an instruction decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.