Bit slice multiplication circuit
US4811269A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 8, 1986 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Oct 8, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3896
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.