Merged CCD/MOS integrated circuit
US4811270A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 1985 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Oct 17, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital integrated circuit that includes on a common substrate both charge-coupled device (CCD) circuitry and metal-oxide semiconductor (MOS) circuitry that combine together efficiently to implement a complex digital function such as a multi-bit multiplier or divider. The CCD circuitry includes an array of full adder cells and the MOS circuitry selectively processes and channels certain bits of a plurality of digital input bits to the individual full adder cells, such processing being based on other of the digital input bits. The introduction of MOS logic into the CCD circuit permits greater flexibility in the layout and interconnection of the individual full adder cells and permits the utilization of more efficient algorithms than otherwise could be used in circuits having CCD elements alone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.