Apparatus and method for an extended arithmetic logic unit for expediting selected floating point operations
US4811272A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1987 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | May 15, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for expediting the alignment of the fraction portion of operands in floating point operations. The alignment is performed in the arthmetic logic unit where the argument of the operand A exponent is subtracted from the argument of the operand B exponent. Because the result B-A can be a negative quantity, the result A-B can also be required. The arthmetic logic unit of the present invention provides additional apparatus for simultaneously determining B-A and A-B. The additional apparatus includes components in the propagate bit and generate bit cell for determining an auxiliary generate bit; an additional carry-chain array for combining the carry-in signal, the propagate bit and the auxiliary generate bit; and selection circuits for selecting the appropriate result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.