Analog storage integrated circuit
US4811285A · kind A · utility
110Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1988 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Jan 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.