Boundary-free semiconductor memory device
US4811297A · kind A · utility
21Cited by
4References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 14, 1987 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Dec 14, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An entire chip is divided into N blocks (N=n.times.m) in accordance with a desired rectangular group of bits (n.times.m bits). The same row decoder is provided for every m blocks, and a row address A.sub.R or a row address A.sub.R+1 adjacent thereto is given to the row decoders. Similarly, the same column decoder is provided for every m blocks, and a column address A.sub.C or a column address A.sub.C +1 adjacent thereto is given to the column decoders. N bits of memory cells are accessed from the blocks, and the accessed memory cells are rearranged, thereby obtaining a desired rectangular group of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.