Semiconductor memory having high-speed serial access scheme
US4811305A · kind A · utility
19Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1987 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Mar 10, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial access semiconductor memory device operable at a high speed and having a large memory capacity is disclosed. The memory device includes a plurality of memory cells divided into a plurality of addresses including an initial address and an end address, a selection circuit for sequentially selecting the memory cells from the initial address towards the end address and a reset circuit for restarting the sequential selection from the initial address, and is featured in that the memory cell or cells of the initial address are of a static type while other memory cells are of a dynamic type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.