Method and apparatus for hybrid I.C. lithography
US4812661A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1986 |
| Grant date | Mar 14, 1989 |
| Priority date | — |
| Expiry date | Aug 20, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J37/3045
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method and apparatus for hybrid integrated circuit lithography wherein an E-beam lithographic exposure is accurately aligned with a preexisting optical lithographic exposure. In one embodiment, the method includes deflecting an E-beam to chip marks while holding the integrated circuit substantially stationary to determine a plurality of deflector parameters, and then moving the integrated circuit while holding the E-beam substantially stationary to determine a number of stage parameters. In a second embodiment, the chip marks are accessed by a combination of stage movements and deflector movements to determine a number of compound parameters. The stage and deflector parameters or, alternatively, the compound parameters, are used to convert the pattern data base of an E-beam machine into a transformed data base which accurately matches the E-beam exposure to the optical exposure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.