Logic circuit connecting input and output signal leads
US4812683A · kind A · utility
10Cited by
8References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 1987 |
| Grant date | Mar 14, 1989 |
| Priority date | — |
| Expiry date | May 19, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0952
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.