Dither circuit using dither including signal component having frequency half of sampling frequency
US4812846A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 1988 |
| Grant date | Mar 14, 1989 |
| Priority date | — |
| Expiry date | Jul 19, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/0639
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A dither circuit for improving linearity in A/D or D/A conversion by adding dither to an input signal of an A/D or D/A converter and subtracting dither from an output signal of the A/D or D/A converter. The dither circuit comprises a 1/2 Fs signal generator for generating a 1/2 Fs signal having a frequency which is 1/2 of a sampling frequency Fs, a noise generator for generating random noise in digital form and an adder for adding the 1/2 Fs signal and the random noise together and supplying a resulting sum signal to the adder and subtractor as dither. According to this invention, a conversion error is reduced with a result that the random noise can be of a small level. Thus, high accuracy requirement in a practical circuit construction is reduced so that the circuit construction is easily performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.