Device for synchronizing the output pulses of a circuit with an input clock
US4813005A · kind A · utility
13Cited by
7References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1987 |
| Grant date | Mar 14, 1989 |
| Priority date | — |
| Expiry date | Jun 24, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31926
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A device for synchronizing the output test pattern signals of a test circuit with the clock signal of a device under test (DUT). The invention uses a programmable delay in the feedback loop of a phase locked loop system to adjust the phase of the test pattern signals to be synchronized with the clock of the device under test (DUT).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.