Multiplier circuit suitable for obtaining a negative product of a multiplier and a multiplicand
US4813008A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1987 |
| Grant date | Mar 14, 1989 |
| Priority date | — |
| Expiry date | Mar 19, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Pi generator receives the multiplier data Y and produces the Pi on the basis of the data Y2i, Y2i+1, and Y2i+2 of three continuous bits of the multiplier data Y (in which, it is defined that Pi=Y2i+Y2i+1-2.multidot.Y2i+2, Pi=Y2i+Y2i+1-2.multidot.Y2i+2' and Y0=0, and i=0, 1, . . . , n/2-1, and Yj is the bit data of the jth bit of the multiplier Y). A partial-product generator receives the Pi from the Pi generator and a multiplicand X, and obtains the partial products X.multidot.Pi of the multiplicand X and the Pi. A partial-product adding circuit weights 2.sup.2i to the partial products X.multidot.Pi derived by the partial-product generator, and adds the resultant data, thereby producing the negative product (-X.multidot.Y) of the multiplicand X and multiplier Y.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.