EEPROM cell with integral select transistor
US4814286A · kind A · utility
31Cited by
12References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 9, 1988 |
| Grant date | Mar 21, 1989 |
| Priority date | — |
| Expiry date | May 9, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
An electrically programmable and electrically erasable floating gate memory device which includes an integrally formed select device. In the n-channel embodiment, a boron region is formed adjacent to the drain region under the control gate and extends slightly under the folating gate. This region is formed using a spacer defined with an anisotropic etching step. The region, in addition to providing enhanced programming, prevents conduction when over-erasing has occurred, that is, when the erasing causes the cell to be depletion-like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.