Method of fabricating semiconductor devices which include vertical elements and control elements
US4814288A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1987 |
| Grant date | Mar 21, 1989 |
| Priority date | — |
| Expiry date | Jul 10, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
A method of fabricating semiconductor devices which include vertical elements and control elements. A well is formed by etching in a semiconductor substrate of a first conductivity type, and a first epitaxial layer having a second conductivity type opposite to the first conductivity type is epitaxially grown, followed by etching and/or grinding and/or polishing to fill said well. Further, a second epitaxial layer of the first conductivity type is epitaxially grown on the substrate and on the first epitaxial layer, and an impurity-doped layer of the second conductivity type for isolation is formed in the second epitaxial layer to penetrate therethrough. A first element is formed in the second epitaxial layer in a portion that corresponds to the well, and a second element having a vertical structure and having a current capability higher than that of the first element is formed except a portion of the second epitaxial layer that corresponds to the well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.