Voltage translator circuit
US4814635A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1987 |
| Grant date | Mar 21, 1989 |
| Priority date | — |
| Expiry date | Nov 27, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage translator circuit generates a predetermined output voltage (e.g. one half of the supply voltage) in response to a predetermined input voltage. A pair of matched field effect transistors are coupled in series between first and second sources of supply voltage. The gate of the load transistor is coupled to a reference voltage, and the gate of the drive transistor is coupled to a source of input voltage. When both transistors are subject to the same operating conditions (at a predetermined input voltage level), their effective resistances become equal and the supply voltage is divided in half. The circuit does not depend for its operation upon precise threshold voltages of the devices as long as the devices are matched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.