Switched impedance comparator
US4814642A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 1987 |
| Grant date | Mar 21, 1989 |
| Priority date | — |
| Expiry date | Sep 10, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356043
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed synchronous comparator circuit, well suited for use in an analog to digital converter. The circuit is switched between acquisition and regeneration modes and includes an amplifier that is operated with positive feedback loop gain in both modes. In the acquisition mode, a relatively low impedance is connected between internal nodes of the amplifier, to improve acquisition speed and keep the positive feedback loop again less than unity. In regeneration mode, the low impedance is disconnected, resulting in a high positive feedback loop again and a desirably amplified output indicative of the polarity of the input differential signal, and the input signal is isolated from the latching nodes. The invention may be implemented in a variety of fabrication technologies, including gallium arsenide field-effect transistors, complementary metal-oxide semiconductor (CMOS) circuitry, and bipolar transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.