Apparatus and method for direct memory to peripheral and peripheral to memory data transfers
US4814977A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1986 |
| Grant date | Mar 21, 1989 |
| Priority date | — |
| Expiry date | Oct 29, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-microprocessor implemented data processing system having a single cycle data transfer capability for its memory mapped peripheral devices is described. A host or controlling microprocessor provides address and control signals for memory accesses. In addition, it also determines that a peripheral operation is desired. When this occurs, a command is sent to the selected peripheral and a memory cycle, fetch or store, for the data transfer is initiated. The address bus is provided with the memory address for the needed data and a special decode that indicates the unique nature of this memory access. Logic circuit means are provided to detect the special decode and to intercept the data bus at the appropriate point in the bus cycle in response thereto. The logic circuit means is adapted to then responsively apply the correct control signals to the peripheral to enable the desired data transfer after the data bus has been intercepted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.