Fabrication of large power semiconductor composite by wafer interconnection of individual devices
US4816422A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1986 |
| Grant date | Mar 28, 1989 |
| Priority date | — |
| Expiry date | Dec 29, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a composite semiconductor from a plurality of substantially identical individual semiconductor devices formed on a common semiconductor wafer includes testing the devices on the wafer to generate a positional mapping of acceptable and non-acceptable devices, dividing the wafer into a plurality of areas of arbitrary size, connecting corresponding contact pads on only the acceptable devices within a given area to each other via common conductive paths which are supported on a dielectric film covering the pads, the film having appropriately located holes filled with conductive material to electrically couple the common conductive paths and the underlying contact pads of only the acceptable devices. The devices within a given area are intercoupled in a manner to form an operational array; single or multiple arrays may be coupled together to form a composite package having common external contacts and heat sink supports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.