Variable speed motor control method and apparatus
US4816723A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 1988 |
| Grant date | Mar 28, 1989 |
| Priority date | — |
| Expiry date | Apr 4, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S388/915
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A motor control method and apparatus employing a speed control loop and a phase control loop, each of which receives a clock signal (F.sub.-- TACH) indicative of the motor's measured phase and rotational frequency, and a synchronizing clock signal (F.sub.-- SYNC) indicative of the desired motor operating speed control loop generates two analog voltage signals, V.sub.-- TACH and V.sub.-- SYNC, from frequency signals F.sub.-- TACH and F.sub.-- SYNC, and generates an error voltage signal proportional to the difference between these two voltage signals. Each frequency signal is first converted into a binary number signal proportional to the associated motor period (inverse frequency). Each such binary number signal is then converted to an analog voltage signal having magnitude proportional to the motor frequency. Each analog voltage signal is thus produced by a two-step process employing the successive reciprocal (division) elements. The nonlinearities introduced by the successive reciprocal elements substantially cancel so that each analog voltage signal is linear with motor speed. The speed, accuracy, and linearity of this frequency-to-voltage conversion method allows continuously va…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.