Synchronizer for a fault tolerant multiple node processing system
US4816989A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1987 |
| Grant date | Mar 28, 1989 |
| Priority date | — |
| Expiry date | Apr 15, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronizer for each node in a multiple node processing system having a message interface for receiving sync and pre-sync time-dependent message, counter means for generating a local time, a time stamp memory having an entry for each node in the multiple node processing system, a time stamper responsive to receiving a time-dependent message from a node for storing the local time in the entry of said time stamp memory for that node to generate a time stamp. The synchronizer has a time stamp voter for generating a medial time stamp value from all the time stamps in the time stamp memory, a sync correction generator for generating a sync delta having a value corresponding to the difference between the voted time stamp and the node's own time stamp, means for adding said sync delta to a nominal transmission timing interval to generate an actual transmission timing interval, and a message generator for generating a pre-sync time dependent message passed to the transmitter at the end of the nominal transmission timing interval and for generating a sync time-dependent message passed to the transmitter at the end of said actual transmission timing interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.