Data processing system with overlap bus cycle operations
US4817037A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1987 |
| Grant date | Mar 28, 1989 |
| Priority date | — |
| Expiry date | Feb 13, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system including several devices connected to an asynchronous communications bus for communications between these devices. The communications bus includes a protocol that requires only a single device to regulate communication between devices at any one time. This regulating device is termed the bus master and the remaining devices are termed slaves. This protocol provides the capability for a slave device to indicate to the bus master that a new bus master is to be designated for a temporary communication. This communication with a different bus master then occurs during the communication of the designated bus master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.