Semiconductor memory with an improved dummy cell arrangement and with a built-in error correcting code circuit
US4817052A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1987 |
| Grant date | Mar 28, 1989 |
| Priority date | — |
| Expiry date | Apr 10, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a read only semiconductor memory, signal lines such as data lines are subjected to an undesired parasitic capacitance which restricts the signal changing rate along the lines. The parasitic capacitance which is driven by a memory cell will become increasingly higher as the memory capacity is increased. According to the present invention, a differential sense amplifier is used to amplify the data signals which are read out of the memory cell. At the same time, a dummy cell is used to generate a reference potential which is to be referred to by the differential sense amplifier. In particular, a dummy cell arrangement is provided wherein each dummy cell includes at least two series-connected semiconductor elements to provide a predetermined dummy cell conductance to establish a reference value. Another aspect of the invention lies in the use of column switches between a common data line and data lines of the memory arrays for coupling only one data line at a time through the column switch to the sense amplifier. In addition, a built-in error-correcting-code circuit is provided which operates in conjunction with a selecting circuit so that memory cells delivering a predetermined set…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.