Fault-tolerant multiprocessor system
US4817091A · kind A · utility
146Cited by
8References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 1987 |
| Grant date | Mar 28, 1989 |
| Priority date | — |
| Expiry date | May 19, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/173
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving the control message from a sending processor module will assume the sending processor module has failed, and operate to take over the task of the failed processor module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.