Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure

US4817093A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Scott Jacobs · Randolph, US
• Maurice T. McMahon · Poughkeepsie, US
• Perwaiz Nihal · Fishkill, US
• Burhan Ozmat · Dallas, US
• Henri D. Schnurmann · Monsey, US
• Arthur R. Zingher · Elmsford, US

Key dates

• Filing date: Jun 18, 1987
• Grant date: Mar 28, 1989
• Expiry date: Jun 18, 2007

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/27
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site. The combination of partitioning along chip boundaries, simple and inexpensive testing without external testers or mainframe computers, and enhanced diagnostics are made possible by the present invention.