Memory back up system with one cache memory and two physically separated main memories
US4819154A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1986 |
| Grant date | Apr 4, 1989 |
| Priority date | — |
| Expiry date | Dec 4, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity. To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory. The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element. The storage operations are carried out by high-speed hardware which stores only t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.