Asynchronous FIFO device comprising a stack of registers having a transparent condition
US4819201A · kind A · utility
Inventors
Key dates
| Filing date | Jul 27, 1987 |
| Grant date | Apr 4, 1989 |
| Priority date | — |
| Expiry date | Jul 27, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/665
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An asynchronous FIFO (firstin, firstout) device suitable for use as a buffer comprises a stack having a plurality of sections. Each section has a data storage register and a control subassembly. Each assembly is associated with one of said data storage registers. A single data input is connected to the first data storage register. The data storage registers have a transparent condition and a latched condition and each subassembly comprises a 2-to-1 MUX (multiplexer) having a first input connected to receive a logic signal indicative of the condition of the preceding subassembly, a second input connected to receive a logic signal indicative of the condition of the following subassembly and an output connected to the associated storage register. The MUX is constructed to deliver on its output a signal representative of the condition of the subassembly and its internal connections are determined by the logic level of the output signal of the MUX.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.