Framer circuit for use in a DTDM network
US4819226A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1987 |
| Grant date | Apr 4, 1989 |
| Priority date | — |
| Expiry date | Nov 10, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/247
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A framer circuit which may be implemented as a single chip is disclosed. The framer circuit performs a number of functions in a DTDM network including generating trains of empty DTDM frames, enabling the writing of data packets into specific DTDM frames and the examination of header data in specific DTDM frames to generate signals for the control of peripheral circuits. The framer circuit comprises an input serial/parallel converter, a frame detection circuit, an output parallel/serial converter and a control unit comprising one or more finite state machines for generating proper control signals such as read and write strobes for data insertion and extraction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.