Isolation of regions in a CMOS structure using selective epitaxial growth
US4820654A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 1987 |
| Grant date | Apr 11, 1989 |
| Priority date | — |
| Expiry date | Dec 9, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76294
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming trench-like isolation structures situated in a semiconductor substrate between adjacent regions of substrate and epitaxial silicon. The trench-like structures include a relatively thick high dielectric constant material enclosed by a relatively thinner pad/buffer dielectric layer. The fabrication of the trench-like isolation regions commences with the formation of recesses with substantially vertical sidewalls into the silicon substrate, the conformal deposition of the relatively thin pad dielectric, and the conformal deposition of a relatively thicker high dielectric constant material. Anisotropic etching is then applied to retain the two dielectric layers along the vertically disposed walls of the recesses. A second conformal deposition of thin pad dielectric, followed by anisotropic etch to expose the substrate at the bottoms of the recesses, results in a sidewall structure with a high dielectric constant material enclosed within pad dielectric material. Selective epitaxial growth of semiconductor from the exposed substrate at the bottoms of the recesses is continued until the recess is substantially full. A planarization of the concluding structure produce…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.