Digital phase lock loop
US4820993A · kind A · utility
11Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1987 |
| Grant date | Apr 11, 1989 |
| Priority date | — |
| Expiry date | Aug 17, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0992
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase lock loop includes a variable precision modular counter which adjusts the output phase by changing the counter modulus by an amount proportional to the current modulus of the counter to preserve the effectiveness of each such change over a wide range of moduli, thereby increasing the effective bandwidth of the digital phase lock loop. The digital phase lock loop is characterized by an exponential duty cycle phase adjustment which avoids spurious oscillations due to either overdamping or resonance, thus increasing loop stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.