Data processing arrangement using an interconnecting network on a single semiconductor chip
US4821176A · kind A · utility
25Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1986 |
| Grant date | Apr 11, 1989 |
| Priority date | — |
| Expiry date | Dec 15, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17368
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing arrangement intended for use, inter alia, in a multi-processing system for use in association with a systolic array is implemented on a single semiconductor chip. The arrangement includes processing means (AU, MU) and storage means (ACC), interconnectable via an electronic equivalent (MM) of a cross-bar switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.