Processor capable of executing one or more programs by a plurality of operation units
US4821187A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1985 |
| Grant date | Apr 11, 1989 |
| Priority date | — |
| Expiry date | Nov 4, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprises first and second operation units, a first program memory which contains first microinstructions for controlling the first operation unit and second microinstructions for controlling at least the second operation units, a second program memory which contains microinstructions for controlling the second operation unit, first control means connected to the first program memory for controlling the first operation unit and the second operation unit, and second control means connected to the second program memory for controlling the second operation unit. In a normal mode, all operation units are under control of the first control means and in a multiprogram mode, the first operation unit is under control of the first control means and the second operation unit is under control of the second control means. These two mode operations are selected in accordance with the microinstructions stored in the first or second program memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.