Arithmetic and logic unit with prior state dependent logic operations
US4821225A · kind A · utility
19Cited by
7References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1987 |
| Grant date | Apr 11, 1989 |
| Priority date | — |
| Expiry date | Apr 27, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/575
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is an arithmetic and logic unit of a microprocessor having hardware improved to execute specified operation such as operation of MAD (modified addition) by a small number of instruction steps. The arithmetic and logic unit of the present invention has a control portion provided with a control circuit for performing the specified operation such as operation of MAD by a small number of instruction steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.