Dual port video memory system having a bit-serial address input port
US4821226A · kind A · utility
123Cited by
12References
8Claims
0Family size
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Key dates
| Filing date | Jan 30, 1987 |
| Grant date | Apr 11, 1989 |
| Priority date | — |
| Expiry date | Jan 30, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual port digital memory system, which includes integral memory sequencing circuitry, is controlled by a bit-serial address and control signal. The address and control signal, which includes a data read address, a data write address and a control value, is serially loaded into a shift register. The address sequencing circuitry loads the read and write address values into integral read and write address registers and, based on the control value, initiates respective read and/or write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.