Parallel channel equalizer architecture
US4821288A · kind A · utility
7Cited by
6References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1987 |
| Grant date | Apr 11, 1989 |
| Priority date | — |
| Expiry date | Dec 21, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Plural n-symbol codewords are helically interleaved and transmitted in a stream. A receiver views the transmitted stream through n time windows, each time window having a length accommodating the longest anticipated decorrelation time of the channel. Individual equalizers process the data in individual windows. The n windows simultaneously furnish the n symbols of each codeword to an error correction decoder. The n equalizers respond to feedback in which the output of the decoder is substituted in place of undecoded symbols from the n windows whenever available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.