Multiple parallel channel equalization architecture
US4821289A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1987 |
| Grant date | Apr 11, 1989 |
| Priority date | — |
| Expiry date | Dec 21, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The n symbols of a codeword of length n are transmitted on n separate channels or frequencies simultaneously. A receiver includes n equalizers that are adapted to receive information from respective ones of the n channels. The outputs of the n equalizers are applied to n inputs of an error correcting decoder which produces the original version of the transmitted codeword. The n equalizers include n feedforward and n feedback transversal filters whose taps are updated by n tap update processors in accordance with a Kalman algorithm, or the like, once each codeword time. The feedforward registers contain successively received signal samples of each of the n channels while the n decision feedback registers contain successively corrected symbols generated at each of the n decoder outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.