Fabrication of FETs with source and drain contacts aligned with the gate electrode
US4822754A · kind A · utility
18Cited by
3References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1984 |
| Grant date | Apr 18, 1989 |
| Priority date | — |
| Expiry date | Jun 12, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a multi-level electrode structure including a gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon is rendered selectively removable in the portion overlying the gate electrode. When this portion is removed, the remaining polycrystalline is aligned with the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.