Processor for expanding a compressed video signal
US4823201A · kind A · utility
94Cited by
16References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1987 |
| Grant date | Apr 18, 1989 |
| Priority date | — |
| Expiry date | Nov 16, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A parallel-pipeline video signal processing system is disclosed which includes a statistical decoder, an arithmetic and logic unit and a pixel interpolator which operate in parallel under the control of sequencing circuitry to expand a compressed video signal. The video signal may have been developed using a variety of compression techniques including Huffman-type statistical encoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.