Plural emitter memory with voltage clamping plural emitter transistor
US4823315A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 1987 |
| Grant date | Apr 18, 1989 |
| Priority date | — |
| Expiry date | May 18, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4116
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transistor memory cell device comprising a pair of cross-coupled transistors constituting storage elements for storing binary information and having column drive emitter inputs to which a relatively high column drive current is applied for the selective read or write operation of storage elements of the cell device. A constant current source provides a relatively low value hold current to maintain the binary digit information stored in the storage elements in the absence of column drive current. A voltage clamping dual emitter transistor has the emitters thereof connected directly to the respective base-collector interconnections of the cross-coupled transistors, with the base of the clamping transistor having applied to it an offset voltage higher than a voltage applied to a non select line connected to the collector circuits of the cross-coupled transistors. This provides a cell device in which the possible forward bias of the cross-coupled transistor pair base-collector junction is small enough to avoid saturation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.