Page mode operation of main system memory in a medium scale computer
US4823324A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1985 |
| Grant date | Apr 18, 1989 |
| Priority date | — |
| Expiry date | Sep 23, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is disclosed which is comprised of a plurality of memory boards each having at least one memory bank associated therewith with each memory bank including a plurality of memory elements addressable by rows and columns. In page-mode operation of the memory device, all of the memory elements receive the active row address strobe signal RAS. The RAS signal is maintained active as long as the memory is to remain in page-mode operation. Memory address information is decoded to select a memory board and a memory bank from the plurality of memory boards and to enable the memory elements to permit either a read or a write operation without the need for performing additional address strobe cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.