Differential amplifier circuit
US4825110A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1986 |
| Grant date | Apr 25, 1989 |
| Priority date | — |
| Expiry date | Oct 9, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A differential amplifier circuit comprising first and second input lines to which potentials with a slight difference therebetween are to be applied, a series combination of a first load transistor and a first amplifier transistor provided between sources of voltage of high and low levels, a series combination of a second load transistor and a second amplifier transistor provided between the sources of the voltages of high and low levels, and activating means provided in association with the first and second amplifier transistors for activating each of the first and second amplifier transistors when the activating means is actuated, each of the first and second load transistors, the first and second amplifier transistors and the activating transistor having a control terminal, the control terminal of the first amplifier transistor being connected to the first input line and the control terminal of the second amplifier transistor being connected to the second input line, characterized by current cutoff means provided in association with the first and second load transistors and responsive to the potentials applied to the first and second input lines, the current cutoff means being o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.