Control means for an integrated memory matrix display and its control process
US4825202A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1987 |
| Grant date | Apr 25, 1989 |
| Priority date | — |
| Expiry date | Apr 30, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/3618
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A control system for an integrated memory matrix display and its associated process is disclosed. The control system for the matrix display utilizes a first group of n row conductors and a second group of m column conductors which carry appropriate signals for excitation of an electro-optical display material at image points which form the integrated memory of a display. A first selection circuit is connected to n' address rows and to n row conductors where n is .ltoreq.2.sup.n' and m read-write circuits, each connected to a column conductor and combine into k packages wherein each package has a maximum of l read-write circuits with the integers m, l and k being such that l is >1 and <m and k is >1 and <m. Each pth read-write circuit of package is connected to the pth row of a bidirectional data bus 21 with l rows, with the p being an integer such that p.gtoreq.1 and .ltoreq.l. Also contained in this system is k processing circuits which are each connected on the one hand to a package of read-write circuits and on the other two a second selection circuit which itself is connected to k' address rows with k being .ltoreq.2.sup.k'.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.