Linear feedback shift register circuit, of systolic architecture
US4825397A · kind A · utility
7Cited by
4References
1Claims
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Key dates
| Filing date | Jun 22, 1987 |
| Grant date | Apr 25, 1989 |
| Priority date | — |
| Expiry date | Jun 22, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/582
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This linear feedback shift register (LFSR) circuit having systolic architecture comprises N cells (C1 to CN) each of which includes an upstream register (e.g. RGE1l ), two operators (e.g. OP1 and OC1l ), and a downstream register (e.g. RGS1). The upstream and downstream registers of each cell are serial shift registers, and their total content is equal to the total number of bits constituting each digital sample processed by the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.