Dynamic decoder circuit with charge-sharing prevention means
US4827160A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 10, 1988 |
| Grant date | May 2, 1989 |
| Priority date | — |
| Expiry date | Mar 10, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic type decoder circuit including a first power source line; a second power source line; and output node; a first transistor connected between the first power source line and the output node, the first transistor being turned on during a reset period to reset the output potential of the output node to a predetermined potential level; a second transistor connected to a second power source line, the second transistor being turned on during a decoding period; a plurality of decoding transistors connected in series between the output node and the second transistor, the decoding transistors being controlled in accordance with address signals; and means for forcibly turning on one or more decoding transistors connected between the output node and the decoding transistor directly connected to the second transistor during the reset period regardless of the potential levels of the address signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.