Transistor sizing system for integrated circuits
US4827428A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1985 |
| Grant date | May 2, 1989 |
| Priority date | — |
| Expiry date | Nov 15, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for improving the design of an integrated circuit by iteratively analyzing the circuit and improving it with each iteration, until a preselected constraint is met. The design improvement is realized by selecting a model for the delay through each active element of the circuit that is characterized by a convex-function of the logarithm of the active element's size. Using the convex function model, with each iteration a static timing analysis of the circuit identifies the output that most grievously violates the specified constraint. With that output selected, an analysis of the path's timing structure identifies the active element in that path whose change in size would yield the largest improvement in performance. The size of that active element is adjusted accordingly and the iteration is repeated. For further improvement, the interconnection pattern of subnetworks of the circuit is evaluated and rearranged to improve performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.