Semiconductor memory including a selectively disabled redunancy circuit
US4827452A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1986 |
| Grant date | May 2, 1989 |
| Priority date | — |
| Expiry date | Aug 7, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a main memory 101 and a spare memory 102. When a part of the memory cells of the main memory 101 are defective, these defective memory cells are replaced by memory cells in the spare memory 102. The space memory 102 is decoded by the decoder circuit 104. The decoder circuit 104 is capable of decoding the spare memory 102 using a signal of an instruction memory 107. The instruction memory 107 is selectively enabled or disabled by an instruction control circuit 108. Consequently, in a state in which the instruction memory 107 is disabled by the control circuit 108, a spare memory selection signal is not provided from the instruction memory 107 to the decoder circuit 104 and the semiconductor memory device normally decodes the main memory including defective memory cells. As a result, the addresses and the like of the defective memory cells can be determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.